CPU Datapath The following figure shows the overall datapath of the simple 5-stage CPU we have learned. Instruction Instr. Decode Fetch Execute Addr. Calc Memory Access Write : Reg. Fetch Вack Next SEQ PC Noxt SEQ PC Next PC RS1 RS2 MUX3 ZEHO? MUXT MUX4 Imm MUX2 Given a memory load instruction, "mov RO; R1+1000]," please give the input that should pe selected at each multiplexer. You can write "none" for che multiplexers that are not used for this nstruction. Ca) MUX1: [b) MUX2: c) MUX3: d) MUX4: WB Data MEM/WB Mamory MUX EX/ MEM ALU MUX MUX ID/EX Sign Extend Reg File IF/ ID Adder Memory Address <

CPU Datapath The following figure shows the overall datapath of the simple 5-stage CPU we have learned. Instruction Instr. Decode Fetch Execute Addr. Calc Memory Access Write : Reg. Fetch Вack Next SEQ PC Noxt SEQ PC Next PC RS1 RS2 MUX3 ZEHO? MUXT MUX4 Imm MUX2 Given a memory load instruction, "mov RO; R1+1000]," please give the input that should pe selected at each multiplexer. You can write "none" for che multiplexers that are not used for this nstruction. Ca) MUX1: [b) MUX2: c) MUX3: d) MUX4: WB Data MEM/WB Mamory MUX EX/ MEM ALU MUX MUX ID/EX Sign Extend Reg File IF/ ID Adder Memory Address <

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 26VE: _____ is a CPU design technique in which instruction execution is divided into multiple stages and...

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