For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively add x30, x28, x29 sli x4, x30, 2 add x3, x4, x10 add x2, x4, x11 1w x30, 0(x3) 1w x31, 0(x2) sub x3, x30, x31 sw x3, 8(x10)
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- For the MIPS assembly instructions below, what is thecorresponding C statement? Assume that the variables f, g, h, i, and j areassigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume thatthe base address of the arrays A and B are in registers $s6 and $s7,respectively. Note: for each line of MIPS code below, write the respective Ccode. After that, write the corresponding C code for the MIPS.sll $t0, $s0, 2add $t0, $s6sll $t1, $s1, 2 add $t1, $s7, $t1lw $s0, 0($t0)addi $t2, $t0, 4lw $t0, 0($t2)add $t0, $t0, $s0sw $t0, 0($t1)For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively: sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 lw x30, 0 (x3) 1w x31, 0 (x4) add x30, x30, x31 sw x30, 16 (x11)For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and 3 are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and 11, respectively. sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 Iw x30, 0(x3) 1w x31, 0(x4) add x30, x30, x31 sw x30, 16 (x11)
- Consider a RISC-V assembly function func1. func1 has three passing arguments stored in registers a0, a1 and a2, uses temporary registers t0-t3 and saved registers s4–s10. func1 needs to call func2 and other functions may call func1 func2 has two passing arguments stored in registers a0 and a1, respectively. In func1, after the program returns to func1 from func2, the code needs the original values stored in registers t1 and a0 before it calls func2. How many words are the stack frames of function func1? Indicate which registers are stored on the stack of func1? pseudo-instructions are not allowed except “j target_label” and “jr ra”.For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively. sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 1w x30, 0 (x3) 1w x31, 0 (x4) add x30, x30, x31 sw x30, 16 (x11)QuedT: Choose the correct answer: [ Opcode, funct3 and funct7/6 in instruction format are used to identify the: (a) function. (b) instruction. (e) branch. (d) memory address. The register that hold the address of the current instruction being executed is called: (a) saved register. (b) global pointer. (e) stack pointer. (d) program counter. Placing the executable file into the memory for execution by the processor is the role of (a) assembler. (b) linker. (e) loader. (d) compiler. The part which responsible for transmitting the data to/from the processor is: (a) control unit. (b) Datapath. (c) data bus. (d) memory. Parallel hardware cannot be used for faster division because: (a) subtraction is conditional on sign of remainder. (b) multiplication is conditional on sign of remainder. (c) subtraction is conditional on sign of divisor. (d) multiplication is conditional on sign of divisor. we cannot slower the clock cycle to fit the floating-point adder algorithm into one clock cycle…
- Complete the following table: MIPS Instruction op code rs rt rd shamt funct imm. /address Hexadecimal Representation add $t4, $s2, $s1 addi $s0, $t0, 123 lw $s6, -88($t7) Note: In MIPS register file, temporary registers $t0-$t7 have indices 8-15 (respec- tively). Also, the saved registers $s0-$s7 have indices 16-23 (respectively).For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers $s0, Ss1, Ss2, $s3, and Ss4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 4-byte words: Show the corresponding C code for each MIPS instruction and write the final C statement. sll St0, Ss3, 2 add St0, St0, $s6 lw St0, 0($t0) sll Stl, Ss4, 2 add St1, Stl, Ss6 lw Stl, 0(St1) add St1, St0, Stl addi St0, Ss7, 32 sw $t1, 0(St0)For each LEGv8 instruction in Exercise 2.9, show the value of the opcode (Op), source register (R_n), and target register (Rd or Rt) fields. For the I-type instructions, shown the value of the immediate field, and for the R-type instructions, show the value of the second source register (Rm). ADDI X9, X6, #8 ADD, X10, X6, XZR STUR X10, [X9, #0] LDUR X9, [X9, #0] ADD X0, X9, X10
- For the following C statement, write the corresponding RISC-V assembly code. Assume that the base addresses of long long int arrays A and B are in registers x6 and x7 respectively. Each element of A or B is 8 bytes, and the variables i and j are assigned to registers x5 and x10 respectively. j = B[A[i*2]] - 16;Determine the value in LR (R14) and PC (R15) when microprocessor is executing theinstruction in Line 21 (SUBS R0, R0, #0x05).Tompute the physical address for the specified operand in each of the following instructions. egister contents and variable are as follows: (CS)=0A00H, (DS)=OB0OH, (SS)=OD00H, S)=OFFOH, (DI)=00BOH, (BP)=00EAH and (UP)=0000H, LIST=00FOH, AX=4020H, BX=2500H. 1) Destination operand of the instruction MOV LIST (BP+DI], AX 2) Source operand of the instruction MOV CL, [BX+200H] 3) Destination operand of the instruction MOV [DI+6400H], DX 4) Source operand of the instruction MOV AL, [BP+SI-400H] 5) Destination operand of the instruction MOV [DI+SP], AX 6) Source operand of the instruction MOV CL, [SP+200H] 7) Destination operand of the instruction MOV [BX+DI+6400H], CX 8) Source operand of the instruction MOV AL , [BP-0200H] 9) Destination operand of the instruction MOV [SI], AX 10) Destination operand of the instruction MOV [BX][DI]+0400H,AL 11) Source operand of the instruction MOV AX, [BP+200H] 12) Source operand of the instruction MOV AL, [SI-0100H] 13) Destination operand of the…