Problem_#08] The waveforms shown below are inputs to a 4-bit binary counter. The input signals represents the clock, count enable, and asynchronous clear. Develop the output waveform.
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- Develop the Q output waveforms for a 74HC190 up/down counter with the input waveforms shown in figure below. A binary 0 is on the data inputs. Start with a count of 0000. CLK CTEN LOADWrite VHDL code for a modulo-13 counter (counting sequence is 010, 110, …. 1210). The counter has the following features: a synchronous Active High Reset a value R can be loaded into the counter, using the signal Ld (Load) The signal Ld is active High Draw the schematic of your counter, showing the inputs and outputs. Show the number of bits for R, Q (output of the counter), Ld.a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate thecomplete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform.(Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.)(Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.)
- a) Design a single-digit decade counter that counts from 0 to 9 and repeats. The single-digit decade counter should be built by a cascaded synchronous binary counter (74LS163) and other basic logic gates. Simulate the complete counter circuit by OrCAD and PSPICE. Capture the circuit schematic and the simulated waveform. (Define the simulation timings for at least one full counting cycle from 0 to 9 and back to 0.) (Hint: Use the DigClock input from the SOURCE as shown below and setup the CLK ONTIME and OFFTIME accordingly for the clock source.) 1/6 Pat DigClock Part List OFFTIME = SuS DSTM1 ONTIME = DELAY= STARTVAL = 0 OPPVAL = 1 Sus EUK FleStim AC Lbrajes Design Cache b) Read the specification of 74LS47 (BCD-to-7-Segment Decoder shown in Appendix) to see how the logic IC operates to drive a 7-segment LED display. Draw the circuit connection of the decade counter in (a) and the decoder to display the count value on the 7-segment LED display. Further explain why common anode…Design counter that counts from 00 to 59, using the IC 74LS90 ripple counter and use two 7 segment display to display the result count. You can also use 7447 binary to 7-segment Display Decoder shown below.A 9-bit asynchronous counter has a 128-kHz clock signal applied. (1) What is the MOD number of this counter? MOD number = (ii) What will be the frequency at the MSB output? fmsb = (iii) Assume that the counter starts at zero. What will be the count after 635 input pulses? After 635 input pulse, Count =
- A certain successive approximation type 8 bit ADC can handle input voltages in the range 0 – 8V. Find, i. The resolution of the ADC. ii. The conversion speed of the ADC for a 1MHZ clock.parity generator design, construct and test a circuit that generates an even parity bit ffrom four messages bits . use XOR gates. adding one more XOR gate, expand the circuit so that it generates an odd parity bit also.III) Convert from Hexadecimal to Decimal (a) 1ACED716 (b) C1AC18A.E8B916 IV) Convert Decimal to Hexadecimal (a) 114510 (b) 3176.5410
- IV) Convert Decimal to Hexadecimal (a) 974510 (b) 2976.5410 V) Convert from Binary to Hexadecimal (a) 10010110101012 (b) 111011101.010101012 VI) Convert from Hexadecimal to Binary (a) 7CAB516 (b) AF2.12B16Q1: Design and draw time diagram of MOD-10 asynchronous/down counter that counts as 0000 to1001 knowing that Clock type is Negative and Output is taken from Q? Q2: Design and draw time diagram of asynchronous/UP counter that counts as 0001 tol001 knowing that Clock type is Negative and Output is taken from Q? Q3: Design 4- bit UP/DOWN Ripple Counter using j-k Flip-FlopProblem #1: 7-4. A binary ripple counter starts from 0 and counts up to 511. (a) What is the MOD number of this counter? (b) How many J-K FFs will be required to design this counter? (c) Find the value of the FFs after 520 input pulses. (d) If the input signal has a frequency of 1024 kHz, what will the fre- quency at the MSB output?