1.2. Fully discuss how interrupts improve the efficiency of the processor; make use of a diagram to show how processor switches between different user programs and 1/O programs during an interruption. 1.3. Discuss in details the difference among programmed 1/0, Interrupt Driven 1/O and Direct Memory access over the processor. 1.4. Discuss in details the difference between multiprocessor and multicore systems.
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- How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency when executing a conditional BRANCH instruction? What techniques can be used to make pipelining more efficient when executing conditional BRANCH instructions?10. Q1 : What is an atomic instruction? Show that if the wait operation is not executed atomically, then mutual exclusion may be violated Q2: What is spinlock? Discuss the advantage and disadvantage of using spinlock. Why do you think Solaris, Linux, and Windows 2000 use spinlocks as a synchronization mechanism only on multiprocessor systems and not on single- processor systems?State the difference between parallel processors & coprocessors.
- The Stack is one of the several forms of memory in an 8086 microprocessor. You are expected to investigate the issues raised below and provide thoughtful answers.1. Provide a scenario in which stack memory and the associated instructions are used (PUSH, POP)417. Each processor in a multiprocessor architecture has its own local memory in a. Tightly coupled systems b. Loosely coupled systems c. Compound couple systems d. Linear couple systemsWhat are the units of a microprocessor? Select one: a. Execution Unit-Bus Interface Unit b. Execution Unit-Bus Interface Unit-Stack c. Execution Unit-Bus Interface Unit-Registers d. Execution Unit-Bus Interface Unit-Flags e. Bus Interface Unit-Registers
- Consider the following scenario. Please share your understanding of a multi-core processor and how it works then explain which student is correct and why. Your post should be at least two paragraphs. Scenario: One friend claims that a dual-core system runs at twice the speed as a single-core system; another friend disagrees by saying that it runs twice as many programs at the same time; a third friend says it runs twice as much data at the same time.1. Draw the complete block diagram for an 8086 Microprocessor system with 8-push button switches and 8-LEDS in detail assuming the input/output (I/O) address is (33h). 2. Redraw the same block diagram if you have 32-switches and 32 -LEDS, starting with the I/O address (1O0h), then write a program to read the switch states and output them to the LEDS in accordance (one to one).A modern computer central processing unit chip (CPU) runs with a clock speed of 2.7 GHz. It can execute one operation in each of these clock cycles. a. How many seconds long is one clock cycle? b. Electrical signals travel at the speed of light. How far can an electrical signal travel in one clock cycle? c. Wires between the CPU's control unit and its cache memory (both on this chip), are about 2 cm long. How does this compare to how far an electrical signal can travel in one clock cycle?
- We want to build a word organized main memory of 8 GB for a 32-bit CPU architecture composed of word organized memory modules of 30-bit address and 8-bit data buses each. a) Draw the interface of the main memory by clearly indicating the widths of the buses. b) Howmanymemorymoduleswouldbenecessarytobuildthememorysystem? c) Design the main memory internal organization built out of the above memory modules (use multiplexers and/or decoders as needed) by clearly indicating the widths of the used busses d) CanweusethismemorysystemasRAMfortheCPUinProblem1?Explainyouranswer.Assume that one 32-bit and two 16-bit microprocessors are to be interfaced to a system bus. The following details are given: All microprocessors have the hardware features necessary for any type of data transfer: programmed I/O, interrupt-driven IO, and DMA. All microprocessors have a 16-bit address bus. Two memory boards, each of 128 KBytes capacity, are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible. The system bus supports a maximum of four interrupt lines and one DMA line. Make any other assumptions necessary, and do the following: a. Give the system bus specifications in terms of number and types of lines. b. Describe a possible protocol for communicating on the bus (i.e., read-write, interrupt, and DMA sequences). c. Explain how the aforementioned devices are interfaced to the system bus.Assume that one 32-bit and two 16-bit microprocessors are to be interfaced to a system bus. The following details are given: 1. All microprocessors have the hardware features necessary for any type of data transfer: programmed I/O, interrupt-driven IO, and DMA. 2. All microprocessors have a 16-bit address bus. 3. Two memory boards, each of 128 KBytes capacity, are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible. 4. The system bus supports a maximum of four interrupt lines and one DMA line. Make any other assumptions necessary, and do the following:a. Give the system bus specifications in terms of number and types of lines. Describe a possible protocol for communicating on the bus (i.e., read-write, interrupt, and DMA sequences). Explain how the aforementioned devices are interfaced to the system bus.