10. To select processors 0 and 8, Which of the following bitwise logical operations is used? A. id & 0= =0 B. id & 1 == 0 C. id & 7==0 D. id & 3= =0
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- 7- In C, to make the first 4 bits port C as input port and the last 4 bits (Most significant) as output, the following command is used: O TRISC=0x003; OTRISC=0X0F; O PORTC=0x00; OPORTC=0X0F; 8 converts analog signal to digital signal so the microcontroller can work with or process that signal. OUSART OFlash memory CADC OTimery of H Q. For the given circuit, which of the following is correct? E OF RAM 256 X 4 A. The number 5 is being written to the memory at address location 203. B. The chip has not been enabled, since the EN terminal is 0; therefore, nothing will be written to the chip and the output is tri- 1 A0 1 A1 O A2 O A3 1 A4 A 255 O A5 1 A6 1 A7 71 QO stated. O DO 1 D1 O D2 1 D3 C. Decimal 10 is being written into memory location 211. D. The read/write line is LOW; therefore, WRITE decimal 5 is being stored at memory O R/W O CS READ EN location 211. Data inputs Address inputs DDDD Data outputsLIST P = 16F877AUsing INCLUDE "P16F877A.INC" and PWM (Pulse Width Modulation), write the microprocessor code that enables the fan to operate at 80% if the button on the 5th bit is pressed, and 30% if the button on the third bit is pressed.
- The effective address of an operand is the value of its actual address in memory.True or False.C++ Program: Make a program that would demonstrate the concept of Line Coding: Polar NRZ: Remember: if next bit is 1, there is inversion if next bit is 0, no inversion neg – means the signal is in the negative axis pos – means the signal is in the positive axis inv – means there is inversion no inv – means there is no inversion a. initially high (starts with positive, inverse is negative) Input: 1 1 1 0 0 1 0 1 1 0 0 0 Output: inv neg inv pos inv neg no inv neg no inv neg inv pos no inv pos inv neg inv pos no inv pos no inv pos no inv pos b. initially low (starts with negative, inverse is positive) Input: 1 1 1 0 0 1 0 1 1 0 0 0 Output: inv pos inv neg inv pos no inv pos no inv pos inv neg no inv neg inv pos inv neg no inv neg no inv neg no inv neg The logic here is when input is 1, next inputted 1 will be inverse…Convert the code from Verilog to Vhdl module wav_player ( input CLK, input switch_play, output reg audio_out ); 1 2 3 4 localparam MEM_SIZE = 36130; // reg [7:0] memory[MEM_SIZE-1:0]; initial begin $readmemh ("01_05_b36130.txt", memory); 8 10 end wire s_start; debouncer dl(.CLK (CLK),..switch_input (switch_play),.trans_up (s_start)); 11 12 13 reg play = 0; reg [5:0] prescaler; 14 15 16 reg [7:0] counter; 17 reg [19:0] address; 18 reg [7:0] value; 19 always e (posedge CLK) begin if (play) 20 21 22 begin prescaler counter); if (counter == 255) begin 30 31 32 33 address <= address + 1; if (address == begin play <= 0; 34 MEM_SIZE) 35 36 37 address <= 38 end 39 end 40 end 41 end 42 if (s_start) 43 begin 44 play <= 1; 45 end 46 end 47
- A set of ten packed BCD numbers is stored in the memory location starting at 3050H. i. Write a program with a subroutine to add these numbers in BCD. If a carry is generated, save it in register B, and adjust it for BCD. The final sum will be less than 9999sCD. ii. Write a second subroutine to unpack the BCD sum stored in registers A and B, and store them in the memory locations starting at 3070H. The most significant digit (BCD4) should be stored at 3070H and the least significant digit (BCD) at 3073H.This flag is used by the instructions that perform BCD (binary .coded decimal) arithmetic Carry Flag O Parity Flag O Auxiliary Carry Flag O the Direction Flag O25: . Find the time delay in the following program if the crystal frequency is 1 MHz. Do not ignore the time delay due to the first and last instruction. DELAY: LDI R16, 30 AGAIN: LDI R17, 35 HERE: NOP NOP DEC R17 BRNE HERE DEC R16 BRNE AGAIN RET 26: Write a program to display 2 on 7 segment. A 7 segment is connected to PortD.
- The C programming language supports these bitwise operators: bitwiseAND, bitwise inclusive OR, bitwise exclusive OR, one's complement (unary). & 1. Identify the corresponding instructions in the AVR Instruction Set Manual that the AVR arithmetic and logic unit (ALU) implements.26. Find the time delay in the following program if the crystal frequency is 1 MHz. Do not ignore the time delay due to the first and last instruction. DELAY: LDI R16, 30 AGAIN: LDI R17, 35 HERE: NOP NOP DEC R17 BRNE HERE DEC R16 BRNE AGAIN RETIn this exercise you are to construct an ALU with the following specification: • The ALU takes 3 different 32-bit inputs: A, B, C; and has one 32-bit output: D. • The ALU supports 7 different operations: – A + B (addition) – A - B (subtraction) – MAX(A,B,C) – MIN(A,B,C) – A & B (bitwise AND) – B & C (bitwise AND) – (A + B) & C (addition followed by bitwise AND) To construct this ALU you will follow a modular design. Assume you have an unlimited number of the following gates and combinational circuits at your disposal, but no others: • 2-arity AND gate, • 2-arity OR gate, • NOT gate, • 2-way MUX, • bit-wise AND circuit: it takes two 32-bit inputs and has a 32-bit output which is the bit-wise AND of its inputs. • 32-bit ADDER: it takes two 32-bit inputs, a 1-bit control signal, and has a 32-bit output. If the control signal is 0, the circuit outs the sum of its inputs. If the control signal is 1, the circuit outputs the difference of its inputs. The inputs and outputs are…