A hypothetical processor has 9 stages of a pipeline as shown in the table below. The first row in the table below shows the pipeline stage number, second row gives the name of each stage, and third row gives the delay of each stage in Nano-seconds. The name of each stage describes the task performed by it. Each stage takes 1 cycle to execute. This processor stores all the register contents in a compressed fashion. After fetching the operands the operands are first decompressed, and before saving the results in register file, the results are first compressed. a)How many cycles are required to execute one instruction on this pipeline? b)How many cycles are required to execute 19 instructions on this pipeline? Assume that no stall cycles occur during the execution of all instructions.
A hypothetical processor has 9 stages of a pipeline as shown in the table below. The first row in the table below shows the pipeline stage number, second row gives the name of each stage, and third row gives the delay of each stage in Nano-seconds. The name of each stage describes the task performed by it. Each stage takes 1 cycle to execute. This processor stores all the register contents in a compressed fashion. After fetching the operands the operands are first decompressed, and before saving the results in register file, the results are first compressed.
a)How many cycles are required to execute one instruction on this pipeline?
b)How many cycles are required to execute 19 instructions on this pipeline? Assume that no stall cycles occur during the execution of all instructions.
c) Assume that all necessary bypass/forwarding circuitry is implemented in this 9 stage pipeline. How many cycles will the pipeline stall during the execution of below given two instructions? Briefly explain your answer.
- X5 = Load from memory
- X2 = X5 + X7
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