Assume that your program has 2400 memory accesses in 20,000 instructions. The instruction cache miss rate is 0.6%, and the data cache miss rate is 6%. The main memory access takes 100 clock cycles on average. The program is executed in a 5-stage pipelined datapath we discussed in Chapter 4. For simplicity, we assume that the data hazards and control hazards have already been fully resolved by using the techniques in Chapter 4 (i.e., it is an ideal pipeline with no additional stalls).  a) What is the actual CPI when considering the potential stalls caused by memory accesses (for both the instruction fetch and data access)?  b) Please discuss a solution to improve the actual CPI discussed in Question (a). Please discuss and justify your solution.

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