Calculate how many clock cycles will take execution of the following segment one RISC-V simple pipeline without forwarding when the outcome of branch instruction is available after EXE stage. Draw the pipelined diagram for this question. lw X1, 0 (X4) 1w X2, 400 (X4) addi X3, X1, X2 SW X3, 0 (X4) sub X4, X4, 4 beq X4, X5, L1

Calculate how many clock cycles will take execution of the following segment one RISC-V simple pipeline without forwarding when the outcome of branch instruction is available after EXE stage. Draw the pipelined diagram for this question. lw X1, 0 (X4) 1w X2, 400 (X4) addi X3, X1, X2 SW X3, 0 (X4) sub X4, X4, 4 beq X4, X5, L1

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Assume a classical RISC pipeline with regular (not delayed) branches. This pipeline has five stages: Instruction Fetch (IF), Instruction Decode (ID), Execute Instruction (EX), Memory Access (MEM), and Writeback (WB). You may assume that there are no resource hazards in this pipeline, but data hazards may exist. Draw a timing diagram that shows the execution of the following instructions in this pipeline. Assume that R1, R2, etc. are registers while A, B, etc. are memory operands. The first operand is the destination while the second operand is the source. The numbers on the left are the addresses of the instructions. BRA is an unconditional branch to a target address 120.
Consider the time required for each MIPS instruction to be executed. Instruction Register write Register read ALU Memory Access fetch TDNT(2020/2021) 50 ns 50 ns 50 ns 50 ns 50 ns 1. Calculate the total time for non-pipelined execution for five (5) instructions 2. Calculate the total time for pipelined execution for five (5) Instructions 3. Calculate the speed-up ratio of the pipelined execution 4. Calculate the speed-up ratio if 100 instructions are added to the above five instructions
MIPS instructions classically take five steps: IF, ID, EX, MEM, WB. A certain MIPS pipeline has the following properties: - IF: 1 cycle - ID: 1 cycle - EX: 1 cycle for A type instructions, 2 cycles for B type instructions, 3 cycles for C type instructions. МЕМ: 1 суcle WB: 1 сycle EX stage of the pipeline has three separate datapaths, to accommodate for the various cycle counts. A-type instructions B-type instructions B-type instructions C-type C-type C-type instructions instructions instructions Run the following instruction sequences through this pipeline with and without forwarding (Assume full data hazard, meaning each instruction depends on data that was produced by the previous instruction, and assume no load/store instructions): a) AAAAAAAABBBBBBBBCCCCCCCC b) АВСАВСАВСАВСАВСАВСАВСАВС с) АСВАСВАСВАСВАСВАСВАСВАСВ
No forwarding is assumed - and assume no hazards are present We will run the following code on the pipeline RISC-V. Please show the values of all the control signals for all the participating instructions only in clock cycle 6. Note that the first instruction (add) is fetched in clock cycle 1. Note that the first instruction (add) is fetched in clock cycle 1 For every pipeline stage write all control signals that are produced or all control signals that are propagated from the previous stage to this one (and which instruction they correspond to), as sketched below. If for a stage and a control signal we do not have anything produced, you can write NA or ---: Fill in the table in picture 2
Consider the following RISC-V assembly instructions: addi x11, x0, 11 addi x2, x0, 1 addi x3, x0, 2 Loop: mul x2, x2, x3 addi x11, x11, -1 bne x11, x0, Loop How many iterations of the loop are performed? What is the value in x2 when this program terminates?
Pipelining with 1-stage Bypass Circuitry: Show the execution of the following sequence of MIPS instructions on a pipeline chart. Also show how source operands of ALUS are gathered for 12, 13, and 14 (i.e. read from the Register File at the Decode stage or forwarded from the first stage of the bypass circuitry) 11: LOAD R1, R8, #100 12: LOAD R2, R8, #500 13: ADD R3, R1, R2 14: STORE R3, R8, #1000
For each of the following sets of RISC-V assembly instructions below, identify any data hazards that occur and indicate which type (i.e., EX hazard 1a or 1b, MEM hazard 2a or 2b, or load-use hazard) of hazard has occurred. You can specify where the hazard has occurred by indicating which instruction (i.e., the first instruction, second instruction, etc.) will experience the hazard. x11, 0(x6) x12, 8(x6) add x20, x11, x12 x20, 0(x6) x13, 16(x6) add x20, x20, x13 x20, 8(x6) ld ld sd ld sd
Create a multi-clock-cycle diagram for the set of RISC-V assembly instructions below. Assume that the datapath implements forwarding and mark all instances where forwarding occurs on the diagram. ld x12, 32(x8) ld x13, 40(x8) add x14, x10, x12 add x14, x13, x14 sd x14, 0(x9)
Consider a Instruction pipeline having 4 phases with duration 20, 40, 50 and 70 ns. Given latch delay is 5 ns. Calculate the following parameters: (i) Pipeline cycle time (ii) Non-pipeline execution time (iii) Speed up ratio (iv) Pipeline time for 1000 tasks (v) Sequential time for 1000 tasks (vi) Throughput Also, draw the block diagram showing the pipelined
Problem 5: Suppose the program counter (PC) is set to 0x60000000hex. a. What range of addresses can be reached using the RISC-V jump-and-link (jal) instruction? (In other words, what is the set of possible values for the PC after the jump instruction executes?) b. What range of addresses can be reached using the RISC-V branch if equal (beq) instruction? (In other words, what is the set of possible values for the PC after the branch instruction executes?)
4 Consider the following RISC-V assembly instructions: addi x11, x0, 11 addi x2, x0, 1 addi x3, x0, 2 Loop: mul x2, x2, x3 addi x11, x11, -1 bne x11, x0, Loop - How many iterations of the loop are performed? - What is the value in x2 when this program terminates? - Provide the format and assembly language instruction for the following hex values: Address 1000: 13 Address 1001: 03 Address 1002: C5 Address 1003: 00 Hint: first consider big-endian vs. little-endian as you convert to binary. Then, divide the bits up into the appropriate fields, decipher the opcode, and so on. 5 :
We have 2 designs D1 and D2 for a synchronous pipeline processor. D1 has 6 stage pipeline with execution times of 1 ns, 3 ns, 2 ns, 4 ns, 2 ns, and 3 ns. While Design D2 has 7 pipeline stages each with 2ns execution time. The delay of an inter-stage register in the pipeline is 1 ns for both D1 and D2. Calculate: 1. Pipeline cycle time for D1 2. Pipeline cycle time for D2 3. Non-pipeline cycle time for D1 4. Non-pipeline cycle time for D2 5. Pipeline time for 500 instructions for D1 6. Pipeline time for 500 instructions for D2 7. Non-pipeline time for 500 instructions for D1 8. Non-pipeline time for 500 instructions for D2 9. How much time can be saved using design D2 over design D1 for executing 500 instructions?