Design and implement in Verilog using gate-level modeling a 4-bit ALU according to the following specifications (see lecture Designing an ALU):Build a 1-bit ALU for bits 0 to 2 (without the SET line, but including the LESS input) as described in class. Your 1-bit ALU is to do ADD, SUBTRACT, AND and OR. Use good hierarchical design (through modules in Verilog) and build most of it from pre-built modules constructed in Project 1.Build a 1-bit ALU for the most significant bit (bit 3), including the SET line, as described in class. Again, use good hierarchical design.Build a 4-bit ALU by instantiating four 1-bit ALU's, as described in class. The first three 1-bit ALU's will be instances of the ALU described in item 1. The fourth 1-bit ALU will be an instance of the ALU from item 2. Your 4-bit ALU is to do ADD, SUBTRACT, AND, OR, and SLT (Set On Less Than). Use good hierarchical design and create a separate module for the 4-bit ALU. Implement the Overflow and Zero outputs of the 4-bit ALU. The overflow may be set only for arithmetic functions (i.e. should be always 0 for the logic functions).Test the 4-bit ALU by adding a test module in Verilog. Make sure to include in the test sequence a few typical examples for each function, including Overflow and Zero.

Answered: Design and implement in Verilog using…

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

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Design and implement in Verilog using gate-level modeling a 4-bit ALU according to the following specifications (see lecture Designing an ALU):

Build a 1-bit ALU for bits 0 to 2 (without the SET line, but including the LESS input) as described in class. Your 1-bit ALU is to do ADD, SUBTRACT, AND and OR. Use good hierarchical design (through modules in Verilog) and build most of it from pre-built modules constructed in Project 1.
Build a 1-bit ALU for the most significant bit (bit 3), including the SET line, as described in class. Again, use good hierarchical design.
Build a 4-bit ALU by instantiating four 1-bit ALU's, as described in class. The first three 1-bit ALU's will be instances of the ALU described in item 1. The fourth 1-bit ALU will be an instance of the ALU from item 2. Your 4-bit ALU is to do ADD, SUBTRACT, AND, OR, and SLT (Set On Less Than). Use good hierarchical design and create a separate module for the 4-bit ALU. Implement the Overflow and Zero outputs of the 4-bit ALU. The overflow may be set only for arithmetic functions (i.e. should be always 0 for the logic functions).
Test the 4-bit ALU by adding a test module in Verilog. Make sure to include in the test sequence a few typical examples for each function, including Overflow and Zero.

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