In this exercise we examine in detail how an instruction is executed in a single- cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word: 10101100100001010000000000011100 Assume that the data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched: R0 R1 R2 R3 R4 R5 R6 R8 R12 R31 0 2 4 6 13 10 12 16 24 31   a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the top of the following Figure) for this instruction word? (Pic3) b. What are the values of ALU control unit’s inputs (ALUOp and Instruction[5-0]) for this instruction?  c. What is the new PC address after this instruction is executed? Highlight the path through which this value is determined.  d. For the ALU and the two add units, what are their data input values?  ALU Add (PC+4) Add (Branch) Input#1 Input#2 Input#1 Input#2 Input#1 Input#2         e. What are the values of all inputs for the “Registers” unit?  Read Reg#1 Read Reg#2 WriteReg WriteData RegWrite

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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In this exercise we examine in detail how an instruction is executed in a single-
cycle datapath. Problems in this exercise refer to a clock cycle in which the
processor fetches the following instruction word:

10101100100001010000000000011100


Assume that the data memory is all zeros and that the processor’s registers have
the following values at the beginning of the cycle in which the above instruction
word is fetched:

R0

R1

R2

R3

R4

R5

R6

R8

R12

R31

0

2

4

6

13

10

12

16

24

31

 

a. What are the outputs of the sign-extend and the jump “Shift-Left-2” (near the top
of the following Figure) for this instruction word? (Pic3)

b. What are the values of ALU control unit’s inputs (ALUOp and Instruction[5-0])
for this instruction? 
c. What is the new PC address after this instruction is executed? Highlight the path
through which this value is determined. 
d. For the ALU and the two add units, what are their data input values? 

ALU

Add (PC+4)

Add (Branch)

Input#1 Input#2

Input#1 Input#2

Input#1 Input#2

 

 

 

 

e. What are the values of all inputs for the “Registers” unit? 

Read Reg#1

Read Reg#2

WriteReg

WriteData

RegWrite

 

 

 

 

 

PC
Instruction [25-01
Add
Read
address
Instruction
[31-0]
Instruction
memory
26
Shift
left 2/
Instruction [31-26]
Instruction [25-21]
Instruction [20-16]
Instruction [15-11]
Instruction [15-01
Jump address [31-01
PC +4 [31-28]
28
Control
RegDst
Jump
Branch
MemRead
MemtoReg
ALUOP
MemWrite
ALUSrc
RegWrite
Read
register 1 Read
data 1
Read
register 2
Write
register
16
Read
data 2
Write
data Registers
Sign-
extend
32
Instruction [5-01
Shift
left 2
ALU
control
Copyright ©2021 Elsevier Inc. All rights reserved
Add
ALU
result
Zero
ALU ALU
result
MUX
Read
Address data
Write Data
data memory
MOX
M
Transcribed Image Text:PC Instruction [25-01 Add Read address Instruction [31-0] Instruction memory 26 Shift left 2/ Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction [15-11] Instruction [15-01 Jump address [31-01 PC +4 [31-28] 28 Control RegDst Jump Branch MemRead MemtoReg ALUOP MemWrite ALUSrc RegWrite Read register 1 Read data 1 Read register 2 Write register 16 Read data 2 Write data Registers Sign- extend 32 Instruction [5-01 Shift left 2 ALU control Copyright ©2021 Elsevier Inc. All rights reserved Add ALU result Zero ALU ALU result MUX Read Address data Write Data data memory MOX M
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