It is now possible to look at the benefits and drawbacks of shared and private L2 caches for single-, multi-, and multi-programmed workloads, and determine whether or not they ought to be re-evaluated now that on-chip L3 caches have been added to the chips. This is possible because on-chip L3 caches have been added to the chips.

It is now possible to look at the benefits and drawbacks of shared and private L2 caches for single-, multi-, and multi-programmed workloads, and determine whether or not they ought to be re-evaluated now that on-chip L3 caches have been added to the chips. This is possible because on-chip L3 caches have been added to the chips.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter11: Operating Systems

Section: Chapter Questions

Problem 30VE

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It is now possible to look at the benefits and drawbacks of shared and private L2 caches for single-, multi-, and multi-programmed workloads, and determine whether or not they ought to be re-evaluated now that on-chip L3 caches have been added to the chips. This is possible because on-chip L3 caches have been added to the chips.
In an x86-64 system, how many shorts can be stored in a cache block if your cache is 8KB (total addressable locations in cache), is 4-way set-associative, and contains 32 sets? Question 3 options: 8 16 32 64
In older processors such as the Intel Pentium or Alpha 21264, the second level of cache was external (located on a diff erent chip) from the main processor and the first level cache. While this allowed for large second level caches, the latency to access the cache was much higher, and the bandwidth was typically lower because the second level cache ran at a lower frequency. Assume a 512 KiB off -chip second level cache has a global miss rate of 4%. If each additional 512 KiB of cache lowered global miss rates by 0.7%, and the cache had a total access time of 50 cycles, how big would the cache have to be to match the performance of the second level direct-mapped cache listed above? Of the eight-way set associative cache?
It's now possible to look at the benefits and drawbacks of shared and private L2 caches for single-, multi-, and multi-programmed workloads, and see if they should be re-evaluated now that on-chip L3 caches have been added to the chips.
We can improve the speed of information transfers across RAM banks by using buffers. Please detail any buffers between the L1 and L2 caches and the L2 cache and the RAM in the aforementioned architecture.
For single, multi, and multiprogrammed work loads, talk about the advantages and downsides of shared vs. private L2 caches. If on-chip L3 caches are now available, it may be time to reconsider these issues.
With the addition of on-chip L3 caches, we may reevaluate the merits of shared and private L2 caches for single-, multi-, and multi-programmed workloads.
A microprocessor with 32-bit address bus has an on-chip 16-KByte four-way set-associative cache memory, the line size is 4 bytes. Draw a block diagram of this cache showing its Organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?
Consider the advantages and disadvantages of shared vs. private L2 caches for single-threaded, multi-threaded, and multiprogrammed workloads, and revisit if on-chip L3 caches are available.
Talk about the pros and cons of shared vs. private L2 caches for single-threaded, multi-threaded, and multiprogrammed tasks and whether they should be looked at again with on-chip L3 caches.
Consider a computer with the following characteristics: total of 4 Mbyte of main memory; word size of 1 byte; block size of 8 bytes; and cache size of 32 Kbytes. For the main memory address of 3BBCAE, give the corresponding tag, cache set, and offset value for a two-way set-associative cache in HEX. You have to show your solution steps.
If on-chip L3 caches are available, should the pros and cons of shared vs. private L2 caches for single- and multi-threaded/multiprogrammed workloads be reconsidered?