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- If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?A computer system has an L1 cache, an L2 cache, and a main memory unit 10.4k view= connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds, 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and the main memory unit respectively. Data Data Bus Bus L1 L2 Main Cache Cache Memory 4 words 4 words When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?Assume the miss rate of an instruction cache is 2% and the miss rate of the data cache is 4%. If a processor has a CPI of 2 without any memory stalls and the miss penalty is 100 cycles for all misses, determine how much faster a processor would run with a perfect cache that never missed. Assume the frequency of all loads and stores is 36%.
- Computer Architecture 2- Consider a computer with the following characteristics: total of 1Mbyte of main memory; word size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes. For the main memory address of BBCAE, give the corresponding tag and offset value for a fully-associative cache. CevapAssume an instruction cache miss rate for an application is 2% and the data cache miss rate of 4% where load and store are 20% of the instruction set. Assume further that our CPU is running at 1 GHz and has a CPI of 2 without any memory stalls The main memory access time is 50 ns. a. Determine the overall CPI with the indicated misses. b. Suppose we like to add a second level cache with an access time of 10 ns which has an instruction miss rate of .4% and data cache miss of 6%. Determine the overall CPI.Desired to have a memory of = 64K bytes.No of bits in address bus to address memory location = 13 bits Maximum memory location addressed by n bits address bus = 2nMaximum memory location addressed by 1 bit address bus = 21 = 2Maximum memory location addressed by 13 bits address bus = 213 = 8192 bytesIn 1 memory chip memory loc...
- Suppose a processor has access to three levels of memory. Level 1 has an access timeof 9 microseconds, level 2 has an access time of 23 microseconds and level 3 has anaccess time of 65 microseconds. Level 1 contains a subset of the bytes contained inlevel 2, and level 2 contains a subset of the bytes contained in level 3. It is estimatedthat 35 % of all requested bytes are contained in level 1, 68 % of all requested bytesare contained in level 2 and 100 % of all requested bytes are contained in level 3. If abyte to be accessed is in level 1, then the processor will directly access it from level 1.If a byte to be accessed is not in level 1 but in level 2, then the processor will directlyaccess it from level 2. If a byte to be accessed is not in level 1 and not in level 2, thenthe processor will directly access it from level 3. For simplicity, we assume that theaccessed bytes are not transferred between the memory levels. Moreover, we ignorethe time that is required for the processor to…Suppose a processor has access to three levels of memory. Level 1 has an access timeof 9 microseconds, level 2 has an access time of 23 microseconds and level 3 has anaccess time of 65 microseconds. Level 1 contains a subset of the bytes contained inlevel 2, and level 2 contains a subset of the bytes contained in level 3. It is estimatedthat 35 % of all requested bytes are contained in level 1, 68 % of all requested bytesare contained in level 2 and 100 % of all requested bytes are contained in level 3. If abyte to be accessed is in level 1, then the processor will directly access it from level 1.If a byte to be accessed is not in level 1 but in level 2, then the processor will directlyaccess it from level 2. If a byte to be accessed is not in level 1 and not in level 2, thenthe processor will directly access it from level 3. For simplicity, we assume that theaccessed bytes are not transferred between the memory levels. Moreover, we ignorethe time that is required for the processor to…Suppose the cache access time is 10ns, main memory access time is 200ns, and the cache hit rate is 95%. Assuming parallel (overlapped) access (or say, load-through is used), what is the average access time for the processor to access an item?
- B- 1. A computer has L1 and L2 caches and main memory. Access to the L1 cache takes 10nanoseconds (ns); access to the L2 cache takes 50 ns; access to the main memory takes100 ns. Suppose L1 cache hit ratio is 0.4 and L2 cache hit ratio is 0.50. What is theeffective access time (EAT) in milliseconds (ms) to access a referenced word on thissystem? (show all calculations involved)6. A given computer has a single cache memory (off-chip) with a 2 ns hit time and a 98% hit rate. Its main memory has 40 ns access time. What is the computer's effective access time? i. ii. If an on-chip cache with a 0.5 ns hit time and a 94% hit rate is added to it, what is the computer's new effective access time? How much of a speedup does the on-chip cache give the computer? iii.Suppose the cache access time is 20ns, main memory access time is 100ns, and the cache hit rate is 90%. Assuming parallel (overlapped) access, what is the average access time for the processor to access an item?