Suppose that the following clock cycles per instruction, and frequencies of usage by a particular program, have been determined for the four instruction types of a system. Instruction type Clock cycles per instruction Frequency A 5 30% в 10% 4. 20% 3 40% A modification to the processor architecture would add a new instruction type E with 3 clock cycles per instruction, at the cost of a 25% increase in the clock cycle time. The cycles per instruction of instruction types A through D are unchanged. On this modified architecture, the program's total instruction count decreases by 20%, and its new instruction frequencies become: Instruction type Frequency A 25% в 10% 15% 30% E 20% By what percentage would the CPU execution time decrease? Give your answer rounded to the nearest integer.

Suppose that the following clock cycles per instruction, and frequencies of usage by a particular program, have been determined for the four instruction types of a system. Instruction type Clock cycles per instruction Frequency A 5 30% в 10% 4. 20% 3 40% A modification to the processor architecture would add a new instruction type E with 3 clock cycles per instruction, at the cost of a 25% increase in the clock cycle time. The cycles per instruction of instruction types A through D are unchanged. On this modified architecture, the program's total instruction count decreases by 20%, and its new instruction frequencies become: Instruction type Frequency A 25% в 10% 15% 30% E 20% By what percentage would the CPU execution time decrease? Give your answer rounded to the nearest integer.

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Suppose that the following clock cycles per instruction, and frequencies of usage by a particular program, have been determined for the four instruction types of a system. Instruction type Clock cycles per instruction Frequency A 5 30% 2 10% 4 20% D 3 40% A modification to the processor architecture would add a new instruction type E with 3 clock cycles per instruction, at the cost of a 25% increase in the clock cycle time. The cycles per instruction of instruction types A through D are unchanged. On this modified architecture, the program's total instruction count decreases by 20%, and its new instruction frequencies become: Instruction type Frequency A 25% 10% 15% D 30% E 20% By what percentage would the CPU execution time decrease? Give your answer rounded to the nearest integer.
Suppose that we are developing a new version of the AMD Barcelona proces- sor with a 4 GHz clock rate. We have added some additional instructions to the instruction set in such a way that the number of instructions has been reduced by 15% from the values shown for each benchmark in Exercise 1.12. The execution times obtained are shown in the following table. a. Name Execution Time (seconds) Reference Time (seconds) bzip2 700 9650 SPECratio 13.7 1.13.2 [10] In general, these CPI values are larger than those obtained in previous exercises for the same benchmarks. This is due mainly to the clock rate used in both cases, 3 GHz and 4 GHz. Determine whether the increase in the CPI is similar to that of the clock rate. If they are dissimilar, why?
ote: sclon Sundwame OT J01n0 Consider the two computers A and B with the clock cycle times 100 ps and 150 ps respectively for some program. The number of cycles per instruction (CPI) for A rnd B are 2.0 and 1.0 respectively for the same program. Which computer is faster and how much? a) A is 1.33 times faster than B b) Bis 1.22 times faste than A c) Ais 1.23 times faster than B d) Bis 1.33 times faster than A Answer Submit
A given processor has 32 registers, uses 16-bit immediate numbers and has 142 instructions in its ISA. In a given program:• 20 % of the instructions take 1 input register and have 1 output register,• 30 % have 2 input registers and 1 output register,• 25 % have 1 input register, 1 output register and take an immediate input as well,• and the remaining 25 % have one immediate input and 1 output register.a) For each of the 4 types of instructions, how many bits are required? Assume that the ISA requires that allinstructions be a multiple of 8 bits in length.b) How much less memory does the program take up if variable-length instruction set encoding is used asopposed to fixed-length encoding?
2. Suppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some program and computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is faster for this program and by how much? ur foverit 10 go
2. Suppose we have two implementations of the same instruction set architecture. Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some program and computer B has a clock cycle time of 500 ps and a CPI of 1.2 for the same program. Which computer is faster for this program and by how much?
1. Suppose you are developing a processor with an execution time of 960 ns, CPIof 1.61, and clock rate of 3 GHz. If the execution time is reduced by an additional 20%without affecting to the CPI and with a clock rate of 4 GHz, determine the number ofinstructions. 2. Determine the clock rate if the CPI is increased by 20% and the CPU time by15% while the number of instructions is unchanged
Determine the effective CPI, MIPS rate, and execution time for this program. Consider two different machines, with two different instruction sets, both of which have a clock rate of 200 MHz. The following measurements are recorded on the two machines running a given set of benchmark programs: Instruction Count (millions) Instruction Type Machine A Arithmetic and logic Load and store Branch Others Machine A Arithmetic and logic Load and store Branch Others 8424 10 9824 Cycles per Instruction 1343 1243 4 a. Determine the effective CPI, MIPS rate, and execution time for each machine. b. Comment on the results.
A computer system contains a big endian byte addressable memory system with 8 separate memory modules. Each memory module is 32 bits wide and contains 134217728 cells. Cells within each memory module are numbered 0 through 134217727. a) If the memory employs high order interleaving, what is the 32-bit memory address of cell 1048578 within module 3? b) If the high order interleaved memory uses little-endian instead of big-endian storage order, what is the 32-bit memory address of cell 511 within module 1? c) If the memory employs low order interleaving, what is the 32-bit memory address of byte 1048575 within module 2? Bytes are numbered starting from 0. Express the address in hex. d) What is the main advantage of using low-order interleaved memory compared to using high-order interleaved memory?
1. A benchmark program is run first on a 200-MHz, and then on a 400-MHz processor. The executed program consists of 200000 instruction executions, with the following instruction mix and clock cycle count: Instruction Type Instruction Count Integer arithmetic Data transfer Floating point Control 100000 60000 30000 10000 (a) Determine the effective CPI for each processor. (b)Determine the MIPS rate for each processor. CPI 1 2 2 2
Problem 6 Assume that the instruction MOV EAX,[EBX+4*ECX] is to be encoded by a Pentium processor operating in the 16 bit instruction mode. Express the instruction in machine code (Hex). ΒΥΤΕ ΒΥΤΕ ΒΥΤΕ BYTE ΒΥΤΕ ΒYΤΕ ΒΥΤΕ 3 4 5. 6. ADDRESS REGISTER SIZE - OPCODE D MOD REG RM SCALE LOW HIGH LOW HIGH SIZE - 67H 66H or SEGM OVERRIDE PREFIX (3 bits) DATA (6 bits) (2 bits) (3 bits) D INDEX ΒΥΤΕ DISP/ DATA DISP/ DATA DATA
A benchmark program is run on a 40 MHz processor. The executed program consist of 100,000 instruction executions, with the following instruction mix and clock cycl count: Instruction Type Instruction Count Cycles per Instruction Integer arithmetic 45,000 1 Data transfer 32,000 2 Floating point 15,000 2 Control transfer 8000 2 Determine the effective CPI, MIPS rate, and execution time for this program.