Processing stages: The processing of an instruction has number of operations. The operations are organized into particular sequence of stages. It attempts to follow a uniform sequence for all instructions. The description of stages are shown below: Fetch: It uses program counter “PC” as memory address to read instruction bytes from memory. The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction. It fetches “valC” that denotes an 8-byte constant. It computes “valP” that denotes value of “PC” plus length of fetched instruction. Decode: The register file is been read with two operands. It gives values “valA” and “valB” for operands. It reads registers with instruction fields “rA” and “rB”. Execute: In this stage the ALU either performs required operation or increments and decrements stack pointer. The resulting value is termed as “valE”. The condition codes are evaluated and destination register is updated based on condition. It determines whether branch should be taken or not in a jump instruction. Memory: The data is been written to memory or read from memory in this stage. The value that is read is determined as “valM”. Write back: The results are been written to register file. It can write up to two results. PC update: The program counter “PC” denotes memory address to read bytes of instruction from memory. It is used to set next instruction’s address.

Question

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Answer 1

Question

Chapter 4.4, Problem 4.28PP

A.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

D.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

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2. [4pts] Use the following C-Code for the problems below. int recFunc (int a, int b) { if (b = 0) == return a; else return 1+recFunc (a, b-1); a. Give the flowchart for the C-Code b. Convert to MIPS assembly and comment each assembly instruction to indicate corresponding C-Code.

Problem I ( Assembler ) Provide the assembly implementation of the C - code below . Sub 10 is a function that subtract 10 from a given input x. Assumption : MyArray base address is store in register $S1. Feel free to use instruction li or si. li load an immediate value into a register . For instance, li $S4 5 will copy value 5 into register $S4. C code for ( i = 0,1 < 10 , i ++ ) { MyArray [ i ] = MyArray [ i - 1 ] + MyArray [ i + 1 ] ; Sub10 ( MyArray [ i ]; } Sub10 ( x ) { Return ( x - 10 ) ; } Code in Assembly Language: sub10(int): ; Implementation of the sub10() function push rbp mov rbp, rsp mov DWORD PTR [rbp-4], edi mov eax, DWORD PTR [rbp-4] sub eax, 10 pop rbp ret main: ; Main function Implementation push rbp mov rbp, rsp sub rsp, 64 mov…

Problem I ( Assembler ) Provide the assembly implementation of the C - code below . Sub 10 is a function that subtract 10 from a given input x. Assumption : MyArray base address is store in register $S1. Feel free to use instruction li or si. li load an immediate value into a register . For instance, li $S4 5 will copy value 5 into register $S4. C code for ( i = 0,1 < 10 , i ++ ) { MyArray [ i ] = MyArray [ i - 1 ] + MyArray [ i + 1 ] ; Sub10 ( MyArray [ i ]; } Sub10 ( x ) { Return ( x - 10 ) ; }

Answer 2

Question

Chapter 4.4, Problem 4.28PP

A.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

D.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

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Answer 3

Question

Chapter 4.4, Problem 4.28PP

A.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

D.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

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Answer 4

Question

Chapter 4.4, Problem 4.28PP

A.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

D.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

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See solution

Answer 5

Chapter 4.4, Problem 4.28PP

A.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

B.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

C.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

D.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 6

Chapter 4.4, Problem 4.28PP

A.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 7

Chapter 4.4, Problem 4.28PP

A.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 8

B.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 9

B.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 10

C.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 11

C.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 12

D.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 13

D.

Program Plan Intro

Processing stages:

The processing of an instruction has number of operations.

The operations are organized into particular sequence of stages.

It attempts to follow a uniform sequence for all instructions.

The description of stages are shown below:

Fetch:

It uses program counter “PC” as memory address to read instruction bytes from memory.

The 4-bit portions “icode” and “ifun” of specifier byte is extracted from instruction.

It fetches “valC” that denotes an 8-byte constant.

It computes “valP” that denotes value of “PC” plus length of fetched instruction.

Decode:

The register file is been read with two operands.

It gives values “valA” and “valB” for operands.

It reads registers with instruction fields “rA” and “rB”.

Execute:

In this stage the ALU either performs required operation or increments and decrements stack pointer.

The resulting value is termed as “valE”.

The condition codes are evaluated and destination register is updated based on condition.

It determines whether branch should be taken or not in a jump instruction.

Memory:

The data is been written to memory or read from memory in this stage.

The value that is read is determined as “valM”.

Write back:

The results are been written to register file.

It can write up to two results.

PC update:

The program counter “PC” denotes memory address to read bytes of instruction from memory.

It is used to set next instruction’s address.

Answer 14

Expert Solution & Answer

Answer 15

Expert Solution & Answer

Answer 16

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Answer 17

Ch. 4.1 - Prob. 4.1PP Ch. 4.1 - Prob. 4.2PP Ch. 4.1 - Prob. 4.3PP Ch. 4.1 - Prob. 4.4PP Ch. 4.1 - Prob. 4.5PP Ch. 4.1 - Prob. 4.6PP Ch. 4.1 - Prob. 4.7PP Ch. 4.1 - Prob. 4.8PP Ch. 4.2 - Practice Problem 4.9 (solution page 484) Write an...Ch. 4.2 - Prob. 4.10PP

Solution Summary: The author explains how the processing of an instruction is organized into specific sequence of stages.

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Chapter 4 Solutions